1. Field
Exemplary embodiments of the present invention relate to a semiconductor design technology, and more particularly, to a semiconductor device including a plurality of conducting lines.
2. Description of the Related Art
In general, the high integration and low power consumption of a semiconductor device has been implemented by the request of users. However, a line width and a pitch of the semiconductor are narrowed as the high integration of the semiconductor device is implemented, and an operation voltage of the semiconductor device is lowered as the semiconductor operates with a low power. Thus, a signal interference generated between signal transmission lines is getting worse, and a malfunction of the semiconductor device may be caused by the signal interference. Generally, the signal interference generated between the signal transmission lines is referred to as a crosstalk.
FIG. 1 is a diagram illustrating an exemplary crosstalk generated between signal lines of a semiconductor device.
Referring to FIG. 1, the semiconductor device includes a plurality of signal lines LINE0 to LINE3 for transmitting a plurality of signals.
The plurality of signal lines LINE0 to LINE3 are arranged, for example, in parallel along a length direction. Since the plurality of signal lines LINE0 to LINE3 are conducting lines, a parasitic capacitor is generated between the signal lines LINE0 to LINE3 and a capacitance of the parasitic capacitor varies depending on disposition of the signal lines LINE0 to LINE3. For example, when a capacitance of a parasitic capacitor generated between the first signal line LINE0 and the second signal line LINE1 is “A*Ct”, a capacitance of a parasitic capacitor generated between the second signal line LINE1 and the third signal line LINE2 is “B*Ct” and a capacitance of a parasitic capacitor generated between the third signal line LINE2 and the fourth signal line LINE3 is “C*Ct” where A, B, and C are coefficients, each capacitance reflected on the second signal line LINE1 and the third signal line LINE2 is greater than each capacitance reflected on the first signal line LINE0 and the fourth signal line LINE3, as shown in table 1 below.
TABLE 1CapacitanceCapacitance of Signal(assumption:Signal LineLineA = B = C = k)LINE0A * Ct1k * CtLINE1(A + B) * Ct2k * CtLINE2(B + C) * Ct3k * CtLINE3C * Ct1k * Ct
In conclusion, the signal interference, which should be prevented, is increased as the capacitance reflected on the signal lines LINE0 to LINE3 is increased.